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chip scale pal/ntsc video encoder with advanced power management adv7174/adv7179 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2002C2009 analog devices, inc. all rights reserved. features itu-r 1 bt601/bt656 ycrcb to pal/ntsc video encoder high quality 10-bit video dacs ssaf? (super sub-alias filter) advanced power management features cgms (copy generation management system) wss (wide screen signaling) ntsc m, pal n 2 , pal b/d/g/h/i, pal-m 3 , pal 60 single 27 mhz clock required (2 oversampling) macrovision 7.1 (adv7174 only) 80 db video snr 32-bit direct digital synthesizer for color subcarrier multistandard video output support: composite (cvbs) component s-video (y/c) video input data port supports: ccir-656 4:2:2 8-bit parallel input format programmable simultaneous composite and s-video or rgb (scart)/ypbpr video outputs programmable luma filters low-pass [pal/ntsc] notch, extended ssaf, cif, and qcif programmable chroma filters (low-pass [0.65 mhz, 1.0 mhz, 1.2 mhz, and 2.0 mhz], cif, and qcif) programmable vbi (vertical blanking interval) programmable subcarrier frequency and phase programmable luma delay individual on/off control of each dac ccir and square pixel operation integrated subcarrier locking to external video source color signal control/ burst signal control interlaced/noninterlaced operation complete on-chip video timing generator programmable multimode master/slave operation closed captioning support teletext insertion port (pal-wst) on-board color bar generation on-board voltage reference 2-wire serial mpu interface (i 2 c? compatible and fast i 2 c) single-supply 2.8 v and 3.3 v operation small 40-lead 6 mm 6 mm lfcsp package ?40c to +85c at 3.3 v ?20c to +85c at 2.8 v applications portable video applications mobile phones digital still cameras functional block diagram 9 9 8 10 8 8 8 10 8 8 8 10 10 10 10 10 10 i 2 c mpu port sclock sdata alsb hsync field/vsync blank clock gnd daca(pin29) v ref r set comp 8 8 8 adv7174/adv7179 color data p7?p0 screset/rtc dacb(pin28) dacc(pin24) v aa y u v reset teletext insertion block yuv to rbg matrix voltage reference circuit real-time control circuit 10-bit dac 10-bit dac 10-bit dac m u l t i p l e x e r cgms and wss insertion block add sync add burst inter- polator sin/cos dds block video timing generator programmable luminance filter programmable chrominance filter inter- polator power management control (sleep mode) ycrcb to yuv matrix 4:2:2 to 4:4:4 inter- polator ttxreq ttx 10 10 10 u v 02980-a-001 figure 1. 1 itu-r and ccir are used interchangeably in this document (itu-r has replaced ccir recommendations). 2 throughout the document, n is referenced to pal C combination C n. 3 adv7174 only. the macrovision anticopy process is licensed for noncommercial home use only, which is its sole intended use in the device. con tact the sales office for the latest macrovision version available.
adv7174/adv7179 rev. b | page 2 of 52 table of contents specifications ..................................................................................... 4 2.8 v specifications ...................................................................... 4 2.8 v timing specifications ........................................................ 5 3.3 v specifications ...................................................................... 6 3.3 v timing specifications ........................................................ 7 absolute maximum ratings ............................................................ 9 esd caution .................................................................................. 9 pin configuration and function descriptions ........................... 10 general description ....................................................................... 11 data path description ................................................................ 11 internal filter response ............................................................. 11 typical performance characteristics ........................................... 13 features ............................................................................................ 16 color bar generation ................................................................ 16 square pixel mode ...................................................................... 16 color signal control .................................................................. 16 burst signal control ................................................................... 16 ntsc pedestal control ............................................................. 16 pixel timing description .......................................................... 16 8-bit ycrcb mode ................................................................. 16 subcarrier reset .......................................................................... 16 real-time co ntrol ..................................................................... 16 video timing description .................................................... 16 vertical blanking data insertion.......................................... 17 mode 0 (ccir-656): slave option ....................................... 17 mode 0 (ccir-656): master option ................................... 17 mode 1: slave option hsync , blank , field ............... 20 mode 1: master option hsync , blank , field ............ 21 mode 2: slave option hsync , vsync , blank ............. 22 mode 2: master option hsync , vsync , blank .......... 23 mode 3: master/slave option hsync , blank , field . 24 power-on reset .......................................................................... 25 sch phase mode ........................................................................ 25 mpu port description ............................................................... 25 register accesses ........................................................................ 26 register programming ................................................................... 27 subaddress register (sr7Csr0) ............................................... 27 register select (sr5Csr0) ......................................................... 27 mode register 1 (mr1) ............................................................. 29 mode register 2 (mr2) ............................................................. 30 mode register 3 (mr3) ............................................................. 31 mode register 4 (mr4) ............................................................. 32 timing mode register 0 (tr0) ................................................ 33 timing mode register 1 (tr1) ................................................ 34 subcarrier frequency registers 3C0 ........................................ 35 subcarrier phase register .......................................................... 35 closed captioning even field data registers 1C0 ................ 35 closed captioning odd field data registers 1C0 ................. 36 ntsc pedestal/pal teletext control registers 3C0 ............. 36 teletext request control register (tc07) .............................. 37 cgms_wss register 0 (c/w0) ............................................... 37 cgms_wss register 1 (c/w1) ............................................... 38 cgms_wss register 2 (c/w2) ............................................... 38 appendix 1board design and layout considerations .......... 39 ground planes ............................................................................ 39 power planes ............................................................................... 39 supply decoupling ..................................................................... 40 digital signal interconnect ....................................................... 40 analog signal interconnect....................................................... 40 appendix 2closed captioning ................................................. 41
adv7174/adv7179 rev. b | page 3 of 52 appendix 3copy generation management system (cgms) ............................................................................................................ 42 function of cgms bits .............................................................. 42 appendix 4wide screen signaling (wss) ............................... 43 function of wss bits .................................................................. 43 appendix 5teletext ..................................................................... 44 teletext insertion......................................................................... 44 teletext protocol .......................................................................... 44 appendix 6waveforms ............................................................... 45 ntsc waveforms (with pedestal) ............................................ 45 ntsc waveforms (without pedestal) ...................................... 46 pal waveforms ........................................................................... 47 pb pr waveforms ......................................................................... 48 appendix 7optional output filter ........................................... 49 appendix 8recommended register values............................. 50 outline dimensions ........................................................................ 52 ordering guide ........................................................................... 52 revision history 4/09rev. a to rev. b changes to power-on reset section ............................................ 25 changes to figure 55 ...................................................................... 40 changes to figure 69, figure 70, and figure 72 .......................... 47 changes to figure 81 caption ....................................................... 52 changes to ordering guide ........................................................... 52 2/04changed from rev. 0 to rev a. added 2.8 v version .......................................................... universal format updated.................................................................. universal device currents updated on 3.3 v specification .......... universal added new table 1 and renumbered subsequent tables ............. 4 added new table 2 and renumbered subsequent tables ........... 5 change to figure 54 ........................................................................ 38 change to figure 55 ........................................................................ 39 change to figure 79 ........................................................................ 48 changed ordering guide temperature specifications .............. 52 updated outline dimensions ........................................................ 52 10/02revision 0: initial version
adv7174/adv7179 rev. b | page 4 of 52 specifications 2.8 v specifications v aa = 2.8 v, v ref = 1.235 v, r set = 150 . all specifications t min to t max 1 , unless otherwise noted. table 1. parameter conditions 1 min typ max unit static performance 2 resolution (each dac) 10 bits accuracy (each dac) integral nonlinearity r set = 300 3.0 lsb differential nonlinearity guaranteed monotonic 1 lsb digital inputs 2 input high voltage, v inh 1.6 v input low voltage, v inl 0.7 v input current, i in v in = 0.4 v or 2.4 v 1 a input capacitance, c in 10 pf digital outputs 2 output high voltage, v oh i source = 400 a 2.4 v output low voltage, v ol i sink = 3.2 ma 0.4 v three-state leakage current 10 a three-state output capacitance 10 pf analog outputs 2 output current 3 r set = 150 , r l = 37.5 33 34.7 37 ma dac-to-dac matching 2.0 % output compliance, v oc 0 1.4 v output impedance, r out 30 k output capacitance, c out i out = 0 ma 30 pf power requirements 2, 4 v aa 2.8 v normal power mode i dac (max) 5 r set = 150 , r l = 37.5 115 120 ma i cct 6 30 ma low power mode i dac (max) 5 62 ma i cct 6 30 ma sleep mode i dac 7 0.1 a i cct 8 0.001 a power supply rejection ratio comp = 0.1 f 0.01 0.5 %/% 1 temperature range t min to t max : C20c to +85c. 2 guaranteed by characterization. 3 dacs can output 35 ma typically at 2.8 v (r set = 150 and r l = 37.5 ). full drive into 37.5 load. 4 power measurements are taken with clock frequency = 27 mhz. max t j = 110c. 5 i dac is the total current (min corresponds to 5 ma output per dac, max corresponds to 37 ma output per dac) to drive all three dacs . turning off individual dacs reduces i dac correspondingly. 6 i cct (circuit current) is the continuous current required to drive the device. 7 total dac current in sleep mode. 8 total continuous current during sleep mode.
adv7174/adv7179 rev. b | page 5 of 52 2.8 v timing specifications v aa = 2.8 v, v ref = 1.235 v, r set = 150 . all specifications t min to t max 1 , unless otherwise noted. table 2. parameter conditions 1 min typ max unit mpu port 2 , 3 sclock frequency 0 400 khz sclock high pulse width, t 1 0.6 s sclock low pulse width, t 2 1.3 s hold time (start condition), t 3 after this period the first cloc k is generated 0.6 s setup time (start condition), t 4 relevant for repeated start condition 0.6 s data setup time, t 5 100 ns sdata, sclock rise time, t 6 300 ns sdata, sclock fall time, t 7 300 ns setup time (stop condition), t 8 0.6 s analog outputs 3 , 4 analog output delay 7 ns dac analog output skew 0 ns clock control and pixel port 4 , 5 f clock 27 mhz clock high time, t 9 8 ns clock low time, t 10 8 ns data setup time, t 11 3.5 ns data hold time, t 12 4 ns control setup time, t 11 4 ns control hold time, t 12 3 ns digital output access time, t 13 12 ns digital output hold time, t 1 4 8 ns pipeline delay, t pd 5 48 clock cycles teletext 3 , 4 , 6 digital output access time, t 16 23 ns data setup time, t 17 2 ns data hold time, t 18 6 ns reset control , 3 4 reset low time 6 ns 1 temperature range t min to t max : C20c to +85c. 2 ttl input values are 0 v to 2.8 v, with input rise/fall times ?3 ns, measured between the 10% and 90% points. timing reference points at 50% for inputs and outputs. analog output load C10 pf. 3 guaranteed by characterization. 4 output delay measured from the 50% point of the rising edge of clock to the 50% point of full-scale transition. 5 see figure 60. 6 teletext port consists of the following: teletext output: ttxreq teletext input: ttx
adv7174/adv7179 rev. b | page 6 of 52 3.3 v specifications v aa = 3.0 vC3.6 v 1 , v ref = 1.235 v, r set = 150 . all specifications t min to t max 2 , unless otherwise noted. table 3. parameter conditions 1 min typ max unit static performance 3 resolution (each dac) 10 bits accuracy (each dac) integral nonlinearity r set = 300 0.6 lsb differential nonlinearity guar anteed monotonic 1 lsb digital inputs 3 input high voltage, v inh 2 v input low voltage, v inl 0.8 v input current, i in 3 , 4 v in = 0.4 v or 2.4 v 1 a input capacitance, c in 10 pf digital outputs 3 output high voltage, v oh i source = 400 a 2.4 v output low voltage, v ol i sink = 3.2 ma 0.4 v three-state leakage current 10 a three-state output capacitance 10 pf analog outputs 3 output current 4 , 5 r set = 150 , r l = 37.5 33 34.7 37 ma output current 6 r set = 1041 , r l = 262.5 5 ma dac-to-dac matching 2.0 % output compliance, v oc 0 1.4 v output impedance, r out 30 k output capacitance, c out i out = 0 ma 30 pf power requirements 3 , 7 v aa 3.0 3.3 3.6 v normal power mode i dac (max) 8 r set = 150 , r l = 37.5 115 120 ma i dac (min) 8 r set = 1041 , r l = 262.5 20 ma i cct 9 35 ma low power mode i dac (max) 8 62 ma i dac (min) 8 20 ma i cct 9 35 ma sleep mode i dac 10 0.1 a i cct 11 0.001 a power supply rejection ratio comp = 0.1 f 0.01 0.5 %/% 1 the max/min specifications are guaranteed over this range. the max/min values are typical over 3.0 v to 3.6 v. 2 temperature range t min to t max : C40c to +85c. 3 guaranteed by characterization. 4 full drive into 37.5 load. 5 dacs can output 35 ma typically at 3.3 v (r set = 150 and r l = 37.5 ), optimum performance obtained at 18 ma dac current (r set = 300 and r l = 75 ). 6 minimum drive current (used with buffered/scaled output load). 7 power measurements are taken with clock frequency = 27 mhz. max t j = 110c. 8 i dac is the total current (min corresponds to 5 ma output per dac, max corresponds to 37 ma output per dac) to drive all three dacs . turning off individual dacs reduces i dac correspondingly. 9 i cct (circuit current) is the continuous current required to drive the device. 10 total dac current in sleep mode. 11 total continuous current during sleep mode.
adv7174/adv7179 rev. b | page 7 of 52 3.3 v timing specifications v aa = 3.0 vC3.6 v 1 , v ref = 1.235 v, r set = 150 . all specifications t min to t max 2 , unless otherwise noted. table 4. parameter conditions 1 min typ max unit mpu port 3 , 4 sclock frequency 0 400 khz sclock high pulse width, t 1 0.6 s sclock low pulse width, t 2 1.3 s hold time (start condition), t 3 after this period, the first cloc k is generated 0.6 s setup time (start condition), t 4 relevant for repeated start condition 0.6 s data setup time, t 5 100 ns sdata, sclock rise time, t 6 300 ns sdata, sclock fall time, t 7 300 ns setup time (stop condition), t 8 0.6 s analog outputs 3 , 5 analog output delay 7 ns dac analog output skew 0 ns clock control and pixel port 4 , 5 f clock 27 mhz clock high time, t 9 8 ns clock low time, t 10 8 ns data setup time, t 11 3.5 ns data hold time, t 12 4 ns control setup time, t 11 4 ns control hold time, t 12 3 ns digital output access time, t 13 12 ns digital output hold time, t 14 8 ns pipeline delay, t pd 6 48 clock cycles teletext 3 , 4 digital output access time, t 16 23 ns data setup time, t 17 2 ns data hold time, t 18 6 ns reset control , 3 4 reset low time 6 ns 1 the maximum/minimum specifications are guaranteed over this range. the maximum/minimum values are typical over 3.0 v to 3.6 v range. 2 temperature range t min to t max : C40c to +85c. 3 ttl input values are 0 v to 3 v, with input rise/fall times ?3 ns, measured between the 10% an d 90% points. timing reference p oints at 50% for inputs and outputs. analog output load C10 pf. 4 guaranteed by characterization. 5 output delay measured from the 50% point of the rising edge of clock to the 50% point of full-scale transition. 6 see figure 60.
adv7174/adv7179 rev. b | page 8 of 52 t 3 t 2 t 6 t 1 t 7 t 5 t 3 t 4 t 8 sdata s clock 02980-0a-002 figure 2. mpu port timing diagram t 9 t 11 clock pixel input data t 10 t 12 hsync, field/vsync, blank hsync, field/vsync, blank cb y cr y cb y t 14 control i/ps control o/ps s t 13 02980-a-003 figure 3. pixel and control data timing diagram t 16 t 17 t 18 ttxreq clock ttx 4 clock cycles 4 clock cycles 4 clock cycles 3 clock cycles 4 clock cycles 02980-a-004 figure 4. teletext timing diagram
adv7174/adv7179 rev. b | page 9 of 52 absolute maximum ratings table 5. parameter rating v aa to gnd 4 v voltage on any digital input pin gnd C 0.5 v to v aa + 0.5 v storage temperature (t s ) ?65c to +150c junction temperature (t j ) 150c lead temperature soldering, 10 sec 260c analog outputs to gnd 1 gnd C 0.5 v to v aa ja 2 30c/w stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability __________________________________________________ 1 analog output short circuit to any power supply or common can be of an indefinite duration. 2 with the exposed metal paddle on the underside of lfcsp soldered to gnd on the pcb. esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
adv7174/adv7179 rev. b | page 10 of 52 pin configuration and fu nction descriptions 37 36 35 38 39 40 33 32 31 34 11 12 13 14 15 16 17 18 19 20 3 4 5 6 7 1 2 10 8 9 26 27 28 29 24 25 22 23 21 30 v ref dac a dac b v aa gnd v aa dac c blank gnd gnd hsync field/vsync alsb c loc k v aa p5 p6 p7 gnd gnd gnd gnd v aa comp sdata sclock gnd v aa gnd reset gnd p4 p3 p2 p1 p0 ttx ttxreq r set screset/ rtc pin 1 indicator adv7174/adv7179 lfcsp top view (not to scale) 02980-a-005 figure 5. pin configurations table 6. pin function descriptions mnemonic input/ output function p7Cp0 i 8-bit 4:2:2 multiplexed ycrcb pixel port (p7Cp0). p0 is the lsb. clock i ttl clock input. requires a stable 27 mhz reference cl ock for standard operation. alternatively, a 24.5454 mhz (ntsc) or 29.5 mhz (pal) can be used for square pixel operation. hsync i/o hsync (modes 1 and 2) control signal. this pin may be co nfigured to output (maste r mode) or accept (slave mode) sync signals. field/ vsync i/o dual function field (mode 1) and vsync (mode 2) control signal. this pin may be configured to output (master mode) or accept (slave mode) these control signals. blank i/o video blanking control signal. the pixel inputs are ig nored when this is logic 0. this signal is optional. screset/rtc i this pin can be configured as an inp ut by setting mr22 and mr21 of mode register 2. it can be configured as a subcarrier reset pin, in which case a low-to-high transi tion on this pin resets th e subcarrier to field 0. alternatively, it can be configured as a real-time control (rtc) input. v ref i/o voltage reference input for dacs or voltage reference output (1.235 v). r set i a 150 resistor connected from this pin to gnd is us ed to control full-scale ampli tudes of the video signals. comp o compensation pin. connect a 0.1 f capacitor from comp to v aa . for optimum dynamic performance in low power mode, the value of the comp capacitor can be lowered to as low as 2.2 nf. dac a o dac output (see table 13 ) dac b o dac output (see table 13 ). dac c o dac output (see table 13 ). sclock i mpu port serial interface clock input. sdata i/o mpu port serial data input/output. alsb i ttl address input. this signal sets up the lsb of the mpu address. reset i this input resets the on-chip timing generator and sets the adv7174/adv7179 into defaul t mode. this is ntsc operation, timing slave mode 0, 8-bit operation, 2 composite out signals. dacs a, b, and c are enabled. ttx i teletext data. ttxreq o teletext data request signal/def aults to gnd when teletext not selected. v aa p power supply (2.8 v or 3.3 v). gnd g ground pin.
adv7174/adv7179 rev. b | page 11 of 52 general description the adv7174/adv7179 is an integrated digital video encoder that converts digital ccir-601 4:2:2 8-bit component video data into a standard analog baseband television signal compatible with worldwide standards. the on-board ssaf (super sub-alias filter) with extended luminance frequency response and sharp stop-band attenuation enables studio quality video playback on modern tvs, giving optimal horizontal line resolution. an advanced power management circuit enables optimal con- trol of power consumption in both normal operating modes and in power-down or sleep modes. the adv7174/adv7179 supports both pal and ntsc square pixel operation. the parts incorporate wss and cgms-a data control generation. the output video frames are synchronized with the incoming data timing reference codes. optionally, the encoder accepts (and can generate) hsync , vsync , and field timing signals. these timing signals can be adjusted to change pulse width and position while the part is in the master mode. the encoder requires a signal two times the pixel rate (27 mhz) clock for standard operation. alternatively, the encoder requires a 24.5454 mhz clock for ntsc or 29.5 mhz clock for pal square pixel mode operation. all internal timing is generated on-chip. a separate teletext port enables the user to directly input teletext data during the vertical blanking interval. the adv7174/adv7179 modes are set up over a 2-wire serial bidirectional port (i 2 c compatible) with two slave addresses. the adv7174/adv7179 is packaged in a 40-lead 6 mm 6 mm lfcsp package. data path description for pal b/d/g/h/i/m/n and ntsc m and n modes, ycrcb 4:2:2 data is input via the ccir-656 compatible pixel port at a 27 mhz data rate. the pixel data is demultiplexed to form three data paths. y typically has a range of 16 to 235, and cr and cb typically have a range of 128 112; however, it is possible to input data from 1 to 254 on both y, cb, and cr. the adv7174/ adv7179 supports pal (b/d/g/h/i/m/n) and ntsc (with and without pedestal) standards. the appropriate sync, blank , and burst levels are added to the ycrcb data. macrovision anti- taping (adv7174 only), closed-captioning, and teletext levels a re also added to y and the resultant data is interpolated to a rate of 27 mhz. the interpolated data is filtered and scaled by three digital fir filters. the u and v s ignals are modulated by the appropriate subcarrier sine/cosine phases and added together to make up the chromi- nance signal. the luma (y) signal can be delayed 1C3 luma cycles (each cycle is 74 ns) with respect to the chroma signal. the luma and chroma signals are then added together to make up the composite video signal. all edges are slew rate limited. the ycrcb data is also used to generate rgb data with appropriate sync and blank levels. the rgb data is in synchronization with the composite video output. alternatively, analog ypbpr data can be generated instead of rgb data. the three l0-bit dacs can be used to output: ? composite video + composite video ? s-video + composite video ? yprpb video ? scart rgb video alternatively, each dac can be individually powered off if not required. video output levels are illustrated in appendix 6 . internal filter response the y filter supports several different frequency responses, including two low-pass responses, two notch responses, an extended (ssaf) response, a cif response, and a qcif response. the uv filter supports several different frequency responses, including four low-pass responses, a cif response, and a qcif response. these can be seen in table 7 and table 8 and figure 6 to figure 18 .
adv7174/adv7179 rev. b | page 12 of 52 table 7. luminance internal filter specifications filter type filter selection pass-band ripple (db) 3 db bandwidth (mhz) stop-band cutoff (mhz) stop-band attenuation (db) mr04 mr03 mr02 low-pass (ntsc) 0 0 0 0.091 4.157 7.37 ?56 low-pass (pal) 0 0 1 0.15 4.74 7.96 ?64 notch (ntsc) 0 1 0 0.015 6.54 8.3 ?68 notch (patl) 0 1 1 0.095 6.24 8.0 ?66 extended (ssaf) 1 0 0 0.051 6.217 8.0 ?61 cif 1 0 1 0.018 3.0 7.06 ?61 qcif 1 1 0 monotonic 1.5 7.15 ?50 table 8. chrominance internal filter specifications filter type filter selection pass-band ripple (db) 3 db bandwidth (mhz) stop-band cutoff (mhz) stop-band attenuation (db) mr07 mr06 mr05 1.3 mhz low-pass 0 0 0 0.084 1.395 3.01 ?45 0.65 mhz low-pass 0 0 1 monotonic 0.65 3.64 ?58.5 1.0 mhz low-pass 0 1 0 monotonic 1.0 3.73 ?49 2.0 mhz low-pass 0 1 1 0.0645 2.2 5.0 ?40 reserved 1 0 0 cif 1 0 1 0.084 0.7 3.01 ?45 qcif 1 1 0 monotonic 0.5 4.08 ?50
adv7174/adv7179 rev. b | page 13 of 52 typical performance characteristics frequency (mhz) 0 01 2 magnitude (db) 46 810 ?10 ?20 ?30 ?50 ?60 ?40 ?70 2 02980-a-006 frequency (mhz) 0 01 2 magnitude (db) 46 810 ?10 ?20 ?30 ?50 ?60 ?40 ?70 2 02980-a-009 figure 6. chrominance internal filter specifications figure 9. pal notch luma filter frequency (mhz) 0 01 2 magnitude (db) 46 810 ?10 ?20 ?30 ?50 ?60 ?40 ?70 2 02980-a-007 frequency (mhz) 0 01 2 magnitude (db) 46 810 ?10 ?20 ?30 ?50 ?60 ?40 ?70 2 02980-a-010 figure 7. pal low-pass luma filter figure 10. extended mode (ssaf) luma filter frequency (mhz) 0 01 2 magnitude (db) 46 810 ?10 ?20 ?30 ?50 ?60 ?40 ?70 2 02980-a-008 frequency (mhz) 0 01 2 magnitude (db) 46 810 ?10 ?20 ?30 ?50 ?60 ?40 ?70 2 02980-a-011 figure 8. ntsc notch luma filter figure 11. cif luma filter
adv7174/adv7179 rev. b | page 14 of 52 frequency (mhz) 0 01 2 magnitude (db) 46 810 ?10 ?20 ?30 ?50 ?60 ?40 ?70 2 02980-a-012 figure 12. qcif luma filter frequency (mhz) 0 01 2 magnitude (db) 46 810 ?10 ?20 ?30 ?50 ?60 ?40 ?70 2 02980-a-013 figure 13. 1.3 mhz low-pass chroma filter frequency (mhz) 0 01 2 magnitude (db) 46 810 ?10 ?20 ?30 ?50 ?60 ?40 ?70 2 02980-a-014 figure 14. 0.65 mhz low-pass chroma filter frequency (mhz) 0 01 2 magnitude (db) 46 810 ?10 ?20 ?30 ?50 ?60 ?40 ?70 2 02980-a-015 figure 15. 1.0 mhz low-pass chroma filter frequency (mhz) 0 01 2 magnitude (db) 46 810 ?10 ?20 ?30 ?50 ?60 ?40 ?70 2 02980-a-016 figure 16. 2.0 mhz low-pass chroma filter frequency (mhz) 0 01 2 magnitude (db) 46 810 ?10 ?20 ?30 ?50 ?60 ?40 ?70 2 02980-a-017 figure 17. cif chroma filter
adv7174/adv7179 rev. b | page 15 of 52 frequency (mhz) 0 01 2 magnitude (db) 46 810 ?10 ?20 ?30 ?50 ?60 ?40 ?70 2 02980-a-018 figure 18. qcif chroma filter
adv7174/adv7179 rev. b | page 16 of 52 features color bar generation the adv7174/adv7179 can be configured to generate 100/ 7.5/75/7.5 color bars for ntsc or 100/0/75/0 for pal color bars. these are enabled by setting mr17 of mode register 1 to logic 1. square pixel mode the adv7174/adv7179 can be used to operate in square pixel mode. for ntsc operation, an input clock of 24.5454 mhz is required. alternatively, for pal operation, an input clock of 29.5 mhz is required. the internal timing logic adjusts accord- ingly for square pixel mode operation. color signal control the color information can be switched on and off the video output using bit mr24 of mode register 2. burst signal control the burst information can be switched on and off the video output using bit mr25 of mode register 2. ntsc pedestal control the pedestal on both odd and even fields can be controlled on a line-by-line basis using the ntsc pedestal control registers. this allows the pedestals to be controlled during the vertical blanking interval. pixel timing description the adv7174/adv7179 operates in an 8-bit ycrcb mode. 8-bit ycrcb mode this default mode accepts multiplexed ycrcb inputs through the p7Cp0 pixel inputs. the inputs follow the sequence cb0, y0 cr0, y1, cb1, y2, and so on. the y, cb, and cr data are input on a rising clock edge. subcarrier reset together with the screset/rtc pin and bits mr22 and mr21 of mode register 2, the adv7174/adv7179 can be used in subcarrier reset mode. the subcarrier resets to field 0 at the start of the following field when a low-to-high transition occurs on this input pin. real-time control together with the screset/rtc pin and bits mr22 and mr21 of mode register 2, the adv7174/adv7179 can be used to lock to an external video source. the real-time control mode allows the adv7174/adv7179 to automatically alter the subcarrier frequency to compensate for line length variation. when the part is connected to a device that outputs a digital data stream in the rtc format (such as a adv7183a video decoder; see figure 19 ), the part automatically changes to the compensated subcarrier frequency on a line-by-line basis. this digital data stream is 67 bits wide and the subcarrier is contained in bits 0 to 21. each bit is two clock cycles long. 00h should be written into all four subcarrier frequency registers when using this mode. video timing description the adv7174/adv7179 is intended to interface with off-the- shelf mpeg1 and mpeg2 decoders. consequently, the adv7174/adv7179 accepts 4:2:2 ycrcb pixel data via a ccir-656 pixel port and has several video timing modes of operation that allow it to be configured as either a system master video timing generator or as a slave to the system video timing generator. the adv7174/adv7179 generates all of the required horizontal and vertical timing periods and levels for the analog video outputs. the adv7174/adv7179 calculates the width and placement of analog sync pulses, blanking levels, and color burst envelopes. color bursts are disabled on appropriate lines, and serration and equalization pulses are inserted where required. in addition, the adv7174/adv7179 supports a pal or ntsc square pixel operation in slave mode. the part requires an input pixel clock of 24.5454 mhz for ntsc and an input pixel clock of 29.5 mhz for pal. the internal horizontal line counters place the various video waveform sections into the correct location for the new clock frequencies. the adv7174/adv7179 has four distinct master and four distinct slave timing configurations. timing control is established with the bidirectional hsync , blank , and field/ vsync pins. timing mode register 1 can also be used to vary the timing pulse widths and where they occur in relation to each other.
adv7174/adv7179 rev. b | page 17 of 52 composite video (e.g., vcr or cable) hsync field/vsync clock green/luma/y red/chroma/pr blue/composite/pb ad7174/adv7179 p7?p0 screset/rtc video decoder (e.g., adv7183a) h/ltransition count start 4 bits reserved 5 bits reserved reset bit 3 sequence bit 2 reserved 14 bits reserved low 128 rtc time slot: 01 14 67 68 not used in the adv7174/adv7179 19 valid sample invalid sample f sc pll increment 1 8/llc 21 0 13 notes 1 f sc pll increment is 22 bits long, value loaded into adv7174/adv7179 f sc dds register is f sc pll increment bits 21:0 plus bits 0:9 of the subcarrier frequency registers. all zeros should be written to the subcarrier frequency registers of the adv7174/adv7179. 2 sequence bit pal: 0 = line normal, 1 = line inverted ntsc: 0 = no change 3 reset bit reset adv7174/adv7179 dds 0 02980-a-019 figure 19. rtc timing and connections vertical blanking data insertion it is possible to allow encoding of incoming ycbcr data on those lines of vbi that do not bear line sync or pre-/post- equalization pulses (see figure 21 to figure 32 ). this mode of operation is called partial blanking and is selected by setting mr32 to 1. it allows the insertion of any vbi data (opened vbi) into the encoded output waveform. this data is present in the digitized incoming ycbcr data stream, for example. wss data, cgms, vps, and so on. alternatively, the entire vbi may be blanked (no vbi data inserted) on these lines by setting mr32 to 0. mode 0 (ccir-656): slave option (timing register 0 tr0 = x x x x x 0 0 0) the adv7174/adv7179 is controlled by the sav (start active video) and eav (end active video) time codes in the pixel data. all timing information is transmitted using a 4-byte synchro- nization pattern. a synchronization pattern is sent immediately before and after each line during active picture and retrace. mode 0 is illustrated in figure 20 . the hsync , field/ vsync , and blank (if not used) pins should be tied high during this mode. mode 0 (ccir-656): master option (timing register 0 tr0 = x x x x x 0 0 1) the adv7174/adv7179 generates h, v, and f signals required for the sav and eav time codes in the ccir-656 standard. the h bit is output on the hsync pin, the v bit is output on the blank pin, and the f bit is output on the field/ vsync pin. mode 0 is illustrated in (ntsc) and (pal). the h, v, and f transitions relative to the video waveform are illustrated in . figure 21 figure 22 figure 23
adv7174/adv7179 rev. b | page 18 of 52 y c r y f f 0 0 0 0 x y 8 0 1 0 8 0 1 0 f f 0 0 f f a b a b a b 8 0 1 0 8 0 1 0 f f 0 0 0 0 x y c b y c r c b y c b y c r eav code sav code ancillary data (hanc) 4 clock 4 clock 268 clock 1440 clock 4 clock 4 clock 280 clock 1440 clock end of active video line start of active video line analog video input pixels ntsc/pal m system (525 llnes/60hz) pal system (625 lines/50hz) y 02980-a-020 figure 20. timing mode 0 (slave mode) 522 523 524 525 1 2 3 4 5 67 8 9 10 11 20 21 22 display display vertical blank odd field even field h v f 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 odd field even field display display vertical blank h v f 02980-a-021 figure 21. timing mode 0 (ntsc master mode)
adv7174/adv7179 rev. b | page 19 of 52 622 623 624 625 1 2 3 4 5 67 21 22 23 display display vertical blank h v f odd field even field 309 310 311 312 314 315 316 317 318 319 320 334 335 336 display display vertical blank h v f odd field even field 313 02980-a-022 figure 22. timing mode 0 (pal master mode) a nalo g video h f v 02980-a-023 figure 23. timing mode 0 data transitions (master mode)
adv7174/adv7179 rev. b | page 20 of 52 mode 1: slave option hsync , blank , field (timing register 0 tr0 = x x x x x 0 1 0) in this mode, the adv7174/adv7179 accepts horizontal sync and odd/even field signals. a transition of the field input when hsync is low indicates a new frame, i.e., vertical retrace. the blank signal is optional. when the blank input is disabled, the adv7174/adv7179 automatically blanks all normally blank lines as per ccir-624. mode 1 is illustrated in (ntsc) and (pal). figure 24 figure 25 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 odd field even field display display hsync blank field 522 523 524 525 1234 5 678 9 10 11 20 21 22 display display odd field even field hsync blank field vertical blank vertical blank 02980-a-024 figure 24. timing mode 1 (ntsc) 622 623 624 625 1 2 3 4 5 67 21 22 23 display odd field even field hsync blank field display 309 310 311 312 313 314 315 316 317 318 319 334 335 336 display odd field even field hsync blank field display 320 vertical blank vertical blank 02980-a-025 figure 25. timing mode 1 (pal)
adv7174/adv7179 rev. b | page 21 of 52 mode 1: master option hsync , blank , field (timing register 0 tr0 = x x x x x 0 1 1) in this mode, the adv7174/adv7179 can generate horizontal sync and odd/even field signals. a transition of the field input when hsync is low indicates a new frame, i.e., vertical retrace. the blank signal is optional. when the blank input is disabled, the adv7174/adv7179 automatically blanks all normally blank lines as per ccir-624. pixel data is latched on the rising clock edge following the timing signal transitions. mode 1 is illustrated in (ntsc) and (pal). illustrates the figure 24 figure 25 figure 26 hsync , blank , and field for an odd or even field transition relative to the pixel data. field pixel data pal = 12 clock/2 n t s c = 1 6 c l o c k /2 pal = 132 clock/2 ntsc = 122 clock/2 cb y cr y hsync blank 02980-a-026 figure 26. timing mode 1 odd/ev en field transitions master/slave
adv7174/adv7179 rev. b | page 22 of 52 mode 2: slave option hsync , vsync , blank (timing register 0 tr0 = x x x x x 1 0 0) in this mode, the adv7174/adv7179 accepts horizontal and vertical sync signals. a coincident low transition of both and vsync inputs indicates the start of an odd field. a vsync low transition when hsync is high indicates the start of an even field. the blank signal is optional. when the blank input is disabled, the adv7174/adv7179 automatically blanks all normally blank lines as per ccir-624. mode 2 is illustrated in (ntsc) and (pal). figure 27 figure 28 522 523 524 525 1 2 3 4 5 6 7 8 9 10 11 20 21 22 display display odd field even field hsync blank vsync 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 odd field even field display display hsync blank vsync vertical blank vertical blank 02980-a-027 figure 27. timing mode 2 (ntsc) 622 623 624 625 1 2 3 4 5 6 7 21 22 23 display odd field even field hsync blank vsync display 309 310 311 312 313 314 315 316 317 318 319 334 335 336 display odd field even field hsync blank display 320 vsync vertical blank vertical blank 02980-a-028 figure 28. timing mode 2 (pal)
adv7174/adv7179 rev. b | page 23 of 52 mode 2: master option hsync , vsync , blank (timing register 0 tr0 = x x x x x 1 0 1) in this mode, the adv7174/adv7179 can generate horizontal and vertical sync signals. a coincident low transition of both hsync and vsync inputs indicates the start of an odd field. a vsync low transition when hsync is high indicates the start of an even field. the blank signal is optional. when the blank input is disabled, the adv7174/adv7179 automatically blanks all normally blank lines as per ccir-624. mode 2 is illustrated in (ntsc) and (pal). illustrates the figure 27 figure 28 figure 29 hsync , blank , and vsync for an even-to- odd field transition relative to the pixel data. illustrates the figure 30 hsync , blank , and vsync for an odd-to- even field transition relative to the pixel data. hsync vsync blank pixel data cb y cr y pal = 12 clock/2 n t s c = 1 6 c l o c k /2 pal = 132 clock/2 ntsc = 122 clock/2 02980-a-029 figure 29. timing mode 2 even-to- odd field transition master/slave vsync pixel data cb y cr y cb hsync blank pal = 12 clock/2 n t s c = 1 6 c l o c k /2 pal = 132 clock/2 ntsc = 122 clock/2 pal = 864 clock/2 ntsc = 858 clock/2 02980-a-082 figure 30. timing mode 2 odd-to-ev en field transition master/slave
adv7174/adv7179 rev. b | page 24 of 52 mode 3: master/slave option hsync , blank , field (timing register 0 tr0 = x x x x x 1 1 0 or x x x x x 1 1 1) in this mode, the adv7174/adv7179 accepts or generates horizontal sync and odd/even field signals. a transition of the field input when hsync is high indicates a new frame, that is, vertical retrace. the blank signal is optional. when the blank input is disabled, the adv7174/adv7179 automatically blanks all normally blank lines as per ccir-624. mode 3 is illustrated in (ntsc) and (pal). figure 31 figure 32 522 523 524 525 1 2 3 4 5 67 8 9 10 11 20 21 22 display display vertical blank odd field even field blank field 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 display display vertical blank hsync odd field blank field hsync even field 02980-a-030 figure 31. timing mode 3 (ntsc) 622 623 624 625 1 2 3 4 5 67 21 22 23 display display vertical blank odd field even field blank field 309 310 311 312 314 315 316 317 318 319 320 334 335 336 display display vertical blank odd field even field 313 hsync blank field hsync 02980-a-031 figure 32. timing mode 3 (pal)
adv7174/adv7179 rev. b | page 25 of 52 power-on reset after power-up, it is necessary to execute a reset operation. a reset occurs on the falling edge of a high-to-low transition on the reset pin. this initializes the pixel port so that the pixel inputs, p7Cp0, are selected. after reset, the adv7174/adv7179 are automatically set up to operate in ntsc mode. subcarrier frequency code 21f07c16h is loaded into the subcarrier frequency registers. all other registers, with the exceptions of mode register 1 and mode register 4, are set to 00h. bit mr44 of mode register 4 is set to logic 1. this enables the 7.5 ire pedestal. bit mr13, dac a, and bit mr16, dac c, are powered down by default. sch phase mode the sch phase is configured in default mode to reset every four (ntsc) or eight (pal) fields to avoid an accumulation of sch phase error over time. in an ideal system, 0 sch phase error would be maintained forever, but in reality, this is impossible to achieve due to clock frequency variations. this effect is reduced by the use of a 32-bit dds, which generates this sch. resetting the sch phase every four or eight fields avoids the accumulation of sch phase error and results in very minor sch phase jumps at the start of the 4- or 8-field sequence. resetting the sch phase should not be done if the video source does not have stable timing or the adv7174/adv7179 is configured in rtc mode (mr21 = 1 and mr22 = 1). under these conditions (unstable video), the subcarrier phase reset should be enabled (mr22 = 0 and mr21 = 1), but no reset applied. in this configuration, the sch phase can never be reset, which means that the output video can now track the unstable input video. the subcarrier phase reset, when applied, resets the sch phase to field 0 at the start of the next field, for example, subcarrier phase reset applied in field 5 (pal) on the start of the next field sch phase is reset to field 0. mpu port description the adv7174/adv7179 supports a 2-wire serial (i 2 c compatible) microprocessor bus driving multiple peripherals. two inputs, serial data (sdata) and serial clock (sclock), carry information between any device connected to the bus. each slave device is recognized by a unique address. the adv7174/adv7179 has four possible slave addresses for both read and write operations. these are unique addresses for each device and are illustrated in figure 33 and figure 34 . the lsb sets either a read or write operation. logic 1 corresponds to a read operation, while logic 0 corresponds to a write operation. a 1 is set by setting the alsb pin of the adv7174/ adv7179 to logic 0 or logic 1. 1 x 10101a1 address control set up by alsb read/write control 0 write 1 read 02980-a-032 figure 33. adv7174 slave address 0 x 10101a1 address control set up by alsb read/write control 0 write 1 read 02980-a-033 figure 34. adv7179 slave address to control the various devices on the bus, the following protocol must be followed: first, the master initiates a data transfer by establishing a start condition, defined by a high-to- low transition on sdata while sclock remains high. this indicates that an address/data st ream will follow. all peripherals respond to the start condition and shift the next eight bits (7-bit address + r/ w bit). the bits transfer from msb down to lsb. the peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. this is known as an acknowledge bit. all other devices withdraw from the bus at this point and maintain an idle condition. the idle condition is where the device monitors the sdata and sclock lines waiting for the start condition and the correct transmitted address. the r/ w bit determines the direction of the data. a logic 0 on the lsb of the first byte means that the master will write information to the peripheral. a logic 1 on the lsb of the first byte means that the master will read information from the peripheral. the adv7174/adv7179 acts as a standard slave device on the bus. the data on the sdata pin is eight bits long, supporting the 7-bit addresses plus the r/ w bit. the adv7174/adv7179 has 26 subaddresses to enable access to the internal registers. it therefore interprets the first byte as the device address and the second byte as the starting subaddress. the subaddresses auto increment allows data to be written to or read from the starting subaddress. a data transfer is always terminated by a stop condition. the user can also access any unique subaddress register on a one-by-one basis without having to update all the registers. there is one exception. the subcarrier frequency registers should be updated in sequence, starting with subcarrier frequency register 0. the auto increment function should then be used to increment and access subcarrier
adv7174/adv7179 rev. b | page 26 of 52 frequency registers 1, 2, and 3. the subcarrier frequency registers should not be accessed independently. figure 35 illustrates an example of data transfer for a read sequence and the start and stop conditions. figure 36 shows bus write and read sequences. st op and start conditions can be detected at any stage during the data transfer. if these conditions are asserted out of sequence with normal read and write operations, they cause an immediate jump to the idle condition. during a given sclock high period, the user should issue only one start condition, one stop condition, or a single stop condition followed by a single start condition. if an invalid subaddress is issued by the user, the adv7174/ adv7179 cannot issue an acknowledge and returns to the idle condition. if in auto-increment mode the user exceeds the highest subaddress, the following action is taken: 1?7 8 9 1 ?7 8 9 1?7 8 9 p s start addr r/w ack subaddress ack data ack stop sdata sclock 02980-a-034 figure 35. bus data transfer register accesses the mpu can write to or read from all of the adv7174/ adv7179 registers except the subaddress register, which is a write-only register. the subaddress register determines which register the next read or write operation accesses. all commu- nications with the part through the bus start with an access to the subaddress register. a read/write operation is performed from to the target address, which then increments to the next address until a stop command on the bus is performed. 1. in read mode, the highest subaddress register contents continues to be output until the master device issues a no- acknowledge. this indicates the end of a read. a no- acknowledge condition is when the sdata line is not pulled low on the ninth pulse. 2. in write mode, the data for the invalid byte is not loaded into any subaddress register, a no-acknowledge is issued by the adv7174/adv7179, and the part returns to the idle condition. data a(s) s slave addr a(s) sub addr a(s) lsb = 0 lsb = 1 data p s slave addr a(s) sub addr a(s) s slave addr a(s) data a(m) data p write sequence read sequence a(s) = no-acknowledge by slave a(m) = no-acknowledge by master a(s) = acknowledge by slave a(m) = acknowledge by master s = start bit p = stop bit a(s) a(m) 02980-a-035 figure 36. write and read sequences
adv7174/adv7179 rev. b | page 27 of 52 register programming this section describes the configuration of each register, including the subaddress register, mode registers, subcarrier frequency registers, the subcarrier phase register, timing registers, closed captioning extended data registers, closed captioning data registers, and ntsc pedestal control registers. subaddress register (sr7Csr0) the communications register is an 8-bit write-only register. after the part has been accessed over the bus and a read/write operation is selected, the subaddress is set up. the subaddress register determines to/from which register the operation takes place. figure 37 shows the various operations under the control of the subaddress register. zero should always be written to sr7Csr6. register select (sr5Csr0) these bits are set up to point to the required starting address. sr4 sr3 sr2 sr1 sr0 sr7 sr6 sr5 zero should be written to these bits sr7 ? sr6(000) power-up values sr5 sr4 sr3 sr2 sr1 sr0 0 0 0 mode register 0 0 0 1 mode register 1 001moderegister2 001moderegister3 000moderegister4 0 0 0 reserved 0 0 1 reserved 001timingmoderegister0 010timingmoderegister1 0 1 0 subcarrier frequency register 0 0 1 1 subcarrier frequency register 1 0 1 1 subcarrier frequency register 2 0 1 0 subcarrier frequency register 3 0 1 0 subcarrier phase register 0 1 1 closed captioning extended data byte 0 0 1 1 closed captioning extended data byte 1 0 0 0 closed captioning data byte 0 0 0 0 closed captioning data byte 1 0 0 1 ntsc pedestal control register 0/ pal ttx control register 0 0 0 1 ntsc pedestal control register 1/ pal ttx control register 1 0 0 0 ntsc pedestal control register 2/ pal ttx control register 2 0 0 0 ntsc pedestal control register 3/ pal ttx control register 3 0 0 1 cgms_wss_0 0 0 1 cgms_wss_1 0 1 0 cgms_wss_2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 11 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 00 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 teletext request control register adv7179 subaddress register sr5 sr4 sr3 sr2 sr1 sr0 adv7174 subaddress register 0 0 0 mode register 0 0 0 0 mode register 1 0 0 1 mode register 2 0 0 1 mode register 3 0 0 0 mode register 4 0 0 0 reserved 0 0 1 reserved 0 0 1 timing mode register 0 0 1 0 timing mode register 1 0 1 0 subcarrier frequency register 0 0 1 1 subcarrier frequency register 1 0 1 1 subcarrier frequency register 2 0 1 0 subcarrier frequency register 3 0 1 0 subcarrier phase register 0 1 1 closed captioning extended data byte 0 0 1 1 closed captioning extended data byte 1 0 0 0 closed captioning data byte 0 0 0 0 closed captioning data byte 1 0 0 1 ntsc pedestal control register 0/ pal ttx control register 0 0 0 1 ntsc pedestal control register 1/ pal ttx control register 1 0 0 0 ntsc pedestal control register 2/ pal ttx control register 2 0 0 0 ntsc pedestal control register 3/ pal ttx control register 3 0 0 1 cgms_wss_0 0 0 1 cgms_wss_1 0 1 0 cgms_wss_2 0 1 0 teletext request control register 0 1 1 reserved 0 1 1 reserved 0 1 0 reserved 0 1 0 reserved 0 1 1 macrovision registers 0 1 1 macrovision registers 1 0 0 macrovision registers 1 0 0 macrovision registers 1 0 1 macrovision registers 1 0 1 macrovision registers 1 0 0 macrovision registers 1 0 0 macrovision registers 1 0 1 macrovision registers 1 0 1 macrovision registers 1 1 0 macrovision registers 1 1 0 macrovision registers 1 1 1 macrovision registers 1 1 1 macrovision registers 1 1 0 macrovision registers 1 1 0 macrovision registers 1 1 1 macrovision registers 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 01 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 11 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 00h 58h 00h 00h 10h 00h 00h 00h 00h 16h 7ch f0h 21h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h macrovision registers 02980-a-036 figure 37. subaddress register map
adv7174/adv7179 rev. b | page 28 of 52 mode register 0 (mr0) bits: mr07 C mr00 address: sr4Csr0 = 00h figure 38 shows the various operations under the control of mode register 0. this register can be read from as well as written to. chroma filter select mr07 mr06 0 0 0 1.3 mhz low-pass filter mr05 0 0 1 0.65 mhz low-pass filter 0 1 0 1.0 mhz low-pass filter 0 1 1 2.0 mhz low-pass filter 1 0 0 reserved 1 0 1 cif 1 1 0 qcif 1 1 1 reserved mr01 mr00 mr07 mr02 mr03 mr05 mr06 mr04 output video standard selection mr01 mr00 0 0 ntsc 0 1 pal (b, d, g, h, and i) 1 0 pal (m) 1 1 reserved luma filter select mr04 mr03 0 0 0 low-pass filter (ntsc) mr02 0 0 1 low-pass filter (pal) 0 1 0 notch filter (ntsc) 0 0 1 notch filter (pal) 1 0 0 extended mode 1 0 1 cif 1 1 0 qcif 1 1 1 reserved 02980-a-037 figure 38. mode register 0 table 9. mr0 bit description bit name bit no. description output video standard selection mr01Cmr00 these bits are used to set up the encode mode. the adv7174/adv7179 can be set up to output ntsc, pal (b/d/g/h/i), and pal (m and n) standard video. pal m is available on the adv7174 only. luminance filter control mr02Cmr04 these bits specify which luminance filter is to be selected. the filter selection is made independent of whether pal or ntsc is selected. chrominance filter control mr05Cmr07 these bits select the chrominance filter. a low-pass filter can be selected with a choice of cutoff frequencies 0.65 mhz, 1.0 mhz, 1.3 mhz, or 2 mhz, along with a choice of cif or qcif filters.
adv7174/adv7179 rev. b | page 29 of 52 mode register 1 (mr1) bits: mr17Cmr10 address: sr4Csr0 = 01h figure 39 shows the various operations under the control of mode register 1. this register can be read from as well as written to. mr11 mr10 mr17 mr12 mr13 mr15 mr16 mr14 closed captioning field selection 0 no data out 0 odd field only 1 even field only 1 0 1 0 1 data out (both fields) mr12 mr11 dac a control 0 normal 1 power-down mr16 reserved dac c control mr13 dac b control mr15 interlace control 0 interlaced 1 noninterlaced mr10 color bar control 0 disable 1 enable mr17 0 normal 1 power-down 0 normal 1 power-down 1 should be written to this bit 02980-a-039 figure 39. mode register 1 table 10. mr1 bit description bit name bit no. description interlace control mr10 this bit is used to set up the output to inte rlaced or noninterlaced mode. power-down mode is relevant only when the part is in composite video mode. closed captioning field selection mr12Cmr11 these bits control the fields on which closed ca ptioning data is displayed; closed captioning information can be displayed on an o dd field, even field, or both fields. dac control mr16Cmr15 and mr13 these bits can be used to power down the dacs. power-down can be used to reduce the power consumption of the adv7174/adv7179 if any of the dacs are not required in the application. reserved mr14 a logic 1 must be written to this register. color bar control mr17 this bit can be used to genera te and output an internal color bar test pattern. the color bar configuration is 100/7.5/75/7.5 for ntsc and 100/ 0/75/0 for pal. it is im portant to note that when color bars are enabled, the adv7174/adv7179 is configured in a master timing mode.
adv7174/adv7179 rev. b | page 30 of 52 mode register 2 (mr2) bits: mr27Cmr20 address: sr4Csr0 = 02h mode register 2 is an 8-bit-wide register. figure 40 shows the various operations under the control of mode register 2. this register can be read from as well as written to. mr21 mr27 mr22 mr23 mr26 mr25 mr24 mr20 chrominance control 0 enable color 1 disable color mr24 genlock control x disable genlock 0 enable subcarrier reset pin 1 0 1 1 enable rtc pin mr22 mr21 low power mode 0 disable 1 enable mr26 square pixel control 0 disable 1 enable mr20 burst control 0 enable burst 1 disable burst mr25 mr27 active video line duration 0 720 pixels 1 710 pixels/702 pixels mr23 reserved 02980-a-039 figure 40. mode register 2 table 11. mr2 bit description bit name bit no. description square pixel control mr20 this bit is used to set up squa re pixel mode. this is available in slave mode only. for ntsc, a 24.5454 mhz clock must be supplied. for pal, a 29.5 mhz clock must be supplied. genlock control mr22Cmr21 these bits control the genlock feature of th e adv7174/ adv7179. setting mr21 to logic 1 configures the screset/rtc pin as an inp ut. setting mr22 to logic 0 configures the screset/rtc pin as a subcarrier reset input. therefore, the subcarrier will reset to field 0 following a low-to-high transition on the screset/rtc pin. setti ng mr22 to logic 1 configures the screset/rtc pin as a real-time control input. active video line duration mr23 this bit switches between two active video line durations. a 0 selects ccir rec601 (720 pixels pal/ntsc), and a 1 selects itu-r.bt470 standard for active video duration (710 pixels ntsc and 702 pixels pal). chrominance control mr24 this bit enables the color in formation to be switched on and off the video output. burst control mr25 this bit enable s the burst information to be switc hed on and off the video output. low power mode mr26 this bit enables the lower power mode of the adv7174/adv7179. this reduces the dac current by 45%. reserved mr27 a logic 0 must be written to this bit.
adv7174/adv7179 rev. b | page 31 of 52 mode register 3 (mr3) bits: mr37Cmr30 address: sr4Csr0 = 03h mode register 3 is an 8-bit-wide register. figure 41 shows the various operations under the control of mode register 3. mr31 mr30 mr37 mr32 mr34 mr33 mr35 mr36 mr30 mr31 reserved vbi_open 0 disable 1 enable mr32 dac output 0 composite 1 green/luma/y mr33 dac a blue/comp/pb blue/comp/pb dac b red/chroma/pr red/chroma/pr dac c chroma output select 0 disable 1 enable mr34 teletext enable 0 disable 1 enable mr35 ttxreq bit mode control 0 normal 1 bit request mr36 input default color 0 disable 1 enable mr37 02980-a-040 figure 41. mode register 3 table 12. mr3 bit description bit name bit no. description revision code mr30Cmr31 these bits are read-o nly and indicate the revision of the device. vbi open mr32 this bit determines whether or not data in the vertical blanking interval (vbi) is output to the analog outputs or blanked. vbi data insertion is not avai lable in slave mode 0. also, when both blank input control and vbi open are enabled, blank input control has priority, i.e., vbi data insertion will not work. dac output mr33 this bit is used to switch th e dac outputs from scart to a euroscart configuration. a complete list of all dac output configurations is shown in table 13 . chroma output select mr34 with this active high bit it is possible to o utput an extra chrominance signal c, on dac a in any configuration that features a cvbs signal. teletext enable mr35 this bit must be set to 1 to enable teletext data insertion on the ttx pin. ttxreq bit mode control mr36 this bit enables switching of the teletext re quest signal from a continuous high signal (mr36 = 0) to a bitwise request signal (mr36 = 1). input default color mr37 this bit determines the default output color from the dacs fo r zero input pixel data (or disconnected). a logic 0 means that the co lor corresponding to 00000000 is displayed. a logic 1 forces the output color to black for 00000000 pixel input video data. table 13. dac output configuration matrix mr34 mr40 mr41 mr33 dac a dac b dac c 0 0 0 0 cvbs cvbs c cvbs: composite video baseband signal y: luminance component signal (for ypbpr or y/c mode) c: chrominance signal (for y/c mode) pb: colorcomponent signal (for ypbpr mode) pr: color component signal (for ypbpr mode) r: red component video (for rgb mode) g: green component video (for rgb mode) b: blue component video (for rgb mode) each dac can be powered on or off individually see mr1 description and figure 39. 0 0 0 1 y cvbs c 0 0 1 0 cvbs cvbs c 0 0 1 1 y cvbs c 0 1 0 0 cvbs b r 0 1 0 1 g b r 0 1 1 0 cvbs pb pr 0 1 1 1 y pb pr 1 0 0 0 c cvbs c 1 0 0 1 y cvbs c 1 0 1 0 c cvbs c 1 0 1 1 y cvbs c 1 1 0 0 c b r 1 1 0 1 g b r 1 1 1 0 c pb pr 1 1 1 1 y pb pr
adv7174/adv7179 rev. b | page 32 of 52 mode register 4 (mr4) bits: mr47Cmr40 address: sr4Csr0 = 04h mode register 4 is an 8-bit-wide register. figure 42 shows the various operations under the control of mode register 4. mr41 mr40 mr47 mr42 mr44 mr43 mr45 mr46 output select 0 yc output 1 rgb/ypbpr output mr40 rgb sync 0 disable 1 enable mr42 pedestal control 0 pedestal off 1 pedestal on mr44 sleep mode control 0 disable 1 enable mr46 active video filter control 0 disable 1 enable mr45 mr47 (0) zero should be written to this bit vsync_3h 0 disable 1 enable mr43 rgb/yuv control 0 rgb output 1 ypbpr output mr41 02980-a-041 figure 42. mode register 4 table 14. mr4 bit description bit name bit no. description output select mr40 this bit sp ecifies if the part is in comp osite video or rgb/ypbpr mode. rgb/ypbpr control mr41 this bit enables the output from the rgb dacs to be set to ypbpr output video standard. rgb sync mr42 this bit is used to set up the rgb outputs with the sync information encoded on all rgb outputs. vsync_3h mr43 when this bit is enabled (1) in sla ve mode, it is possible to drive the vsync active low input for 2.5 lines in pal mode and three lines in ntsc mode. when this bit is enabled in master mode, the adv7174/adv7179 outputs an active low vsync signal for three lines in ntsc mode and 2.5 lines in pal mode. pedestal control mr44 this bit specifies whether a pedestal is to be generated on the ntsc composite video signal. this bit is invalid if the adv7174/ adv 7179 is configured in pal mode. active video filter control mr45 this bit controls the filter mo de applied outside the active video portion of the line. this filter ensures that the sync rise and fall time s are always on spec regardless of which luma filter is selected. a lo gic 1 enables this mode. sleep mode control mr46 when this bit is set (1), sleep mode is enabled. with this mode enabled, the adv7174/adv7179 power consumption is reduced to typically 200 na. the i 2 c registers can be written to and read from when the adv7174/adv7179 is in sleep mode. if mr46 is set to a (0) when the device is in sleep mode, the adv7174/adv7179 comes out of sleep mode and resumes normal operation. also, if the reset signal is applied during sleep mode, the adv7174/adv7179 comes out of sleep mode and resumes normal operation. reserved mr47 a logic 0 should be written to this bit.
adv7174/adv7179 rev. b | page 33 of 52 timing mode register 0 (tr0) bits: tr07Ctr00 address: sr4Csr0 = 07h figure 43 shows the various operations under the control of timing register 0. this register can be read from as well as written to. tr01 tr00 tr07 tr02 tr03 tr05 tr06 tr04 timing register reset tr07 blank input control 0 enable 1 disable tr03 pixel port control 0 8 bit 1 forbidden tr06 master/slave control 0 slave timing 1 master timing tr00 luma delay 0 0ns delay 0 74ns delay 1 148ns delay 1 0 1 0 1 222ns delay tr05 tr04 timing mode selection 0 mode 0 0 mode 1 1 mode 2 1 0 1 0 1 mode 3 tr02 tr01 02980-a-042 figure 43. timing register 0 table 15. tr0 bit description bit name bit no. description master/slave control tr00 this bit controls whether the adv7174/adv7179 is in master or slave mode. timing mode selection tr02Ctr01 these bits control the timing mode of the adv7174/adv7179. these modes are described in more detail in the 3.3 v timing specifications table. blank input control tr03 this bit controls whether the blank input is used when the part is in slave mode. luma delay tr05Ctr04 these bits control the addition of a luminan ce delay. each bit represents a delay of 74 ns. pixel port control tr06 this bit is used to set the pixel port to a ccept 8-bit or ycrcb data on pins p7Cp0. 0 must be written here. timing register reset tr07 toggling the tr07 from low to high and to low again resets the internal timing counters. this bit should be toggled after power-up, reset, or changing to a new timing mode.
adv7174/adv7179 rev. b | page 34 of 52 timing mode register 1 (tr1) bits: tr17Ctr10 address: sr4Csr0 = 08h timing register 1 is an 8-bit-wide register. figure 44 shows the various operations under the control of timing register 1. this register can be read from as well written to. this register can be used to adjust the width and position of the master mode timing signa ls. tr11 tr10 tr17 tr12 tr13 tr15 tr16 tr14 hsync to pixel data adjust tr17 tr16 00 t pclk 1 t pclk 1 t pclk 4 t pclk 16 t pclk 128 t pclk 0 t pclk 4 t pclk 8 t pclk 16 t pclk 1 t pclk 4 t pclk 16 t pclk 128 t pclk 2 t pclk 3 t pclk 0 1 1 0 1 0 1 hsync to field/vsync delay tr13 tr12 0 0 1 1 0 1 0 1 hsync width 0 0 1 1 0 1 0 1 tr11 tr10 hsync to field rising edge delay (mode 1 only) xt b t b + 32 s x 0 1 tr15 tr14 t c t a t b vsync width (mode 2 only) tr15 tr14 0 0 1 1 0 1 0 1 line 313 line 314 line 1 timing mode 1 (master/pal) hsync field/vsync t b t a t c 02980-a-043 figure 44. timing register 1 table 16. tr1 bit description bit name bit no. description these bits adjust the hsync pulse width. hsync width tr11Ctr10 these bits adjust the position of the hsync output relative to the field/ vsync output. hsync to field/ vsync delay tr13Ctr12 when the adv7174/adv7179 is in timing mode 1, these bits adjust the position of the hsync output relative to the field output rising edge. hsync to field rising edge delay tr15Ctr14 when the adv7174/adv7179 is configured in timing mode 2, these bits adjust the vsync pulse width. vsync width tr15Ctr14 this enables the hsync to be adjusted with respect to the pixel data. this allows the cr and cb components to be swapped. this adjustment is available in both master and slave timing modes. hsync to pixel data adjust tr17Ctr16
adv7174/adv7179 rev. b | page 35 of 52 subcarrier frequency registers 3C0 bits: fsc3Cfsc0 address: sr4Csr00 = 09hC0ch these 8-bit-wide registers are used to set up the subcarrier frequency. the value of these registers is calculated by using the following equation: *2 32 line video one in cycles clock mhz 27 of no. line video of line one in values frequency r subcarrie of no. * rounded to the nearest integer. for example, in ntsc mode, eh1c07f21d 569408542 2 1716 5.227 32 = == value frequency subcarrier note that on power-up, f sc register 0 is set to 16h. a value of 1e as derived above is recommended. program as f sc register 0: 1eh f sc register 2: 7ch f sc register 3: f0h f sc register 4: 21h figure 45 shows how the frequency is set up by the four registers. subcarrier frequency reg 3 s ubcarrie r frequency reg 2 s ubcarrie r frequency reg 1 s ubcarrie r frequency reg 0 fsc30 fsc29 fsc27 fsc25 fsc28 fsc24 fsc31 fsc26 fsc22 fsc21 fsc19 fsc17 fsc20 fsc16 fsc23 fsc18 fsc14 fsc13 fsc11 fsc9 fsc12 fsc8 fsc15 fsc10 fsc6 fsc5 fsc3 fsc1 fsc4 fsc0 fsc7 fsc2 02980-a-044 figure 45. subcarrier frequency register subcarrier phase register bits: fp7Cfp0 address: sr4Csr0 = 0dh this 8-bit-wide register is used to set up the subcarrier phase. each bit represents 1.41. for normal operation, this register is set to 00h. closed captioning even field data registers 1C0 bits: ced15Cced0 address: sr4Csr0 = 0ehC0fh these 8-bit-wide registers are used to set up the closed captioning extended data bytes on even fields. figure 46 shows how the high and low bytes are set up in the registers. byte 1 byte 0 ced6 ced5 ced3 ced1 ced4 ced2 ced0 ced7 ced14 ced13 ced11 ced9 ced12 ced10 ced8 ced15 002980-a-045 figure 46. closed captioning extended data register
adv7174/adv7179 rev. b | page 36 of 52 closed captioning odd fi eld data registers 1C0 bits: ccd15Cccd0 subaddress: sr4Csr0 = 10hC11h these 8-bit-wide registers are used to set up the closed captioning data bytes on odd fields. figure 47 shows how the high and low bytes are set up in the registers. byte 1 byte 0 ccd6 ccd5 ccd3 ccd1 ccd4 ccd2 ccd0 ccd7 ccd14 ccd13 ccd11 ccd9 ccd12 ccd10 ccd8 ccd15 002980-a-046 figure 47. closed capt ioning data register ntsc pedestal/pal teletext control registers 3C0 bits: pce15Cpce0, pco15Cpco0/txe15Ctxe0, txo15Ctxo0 subaddress: sr4Csr0 = 12hC15h these 8-bit-wide registers are used to enable the ntsc pedestal/ pal teletext on a line-by-line basis in the vertical blanking interval for both odd and even fields. figure 48 and figure 49 show the four control registers. a logic 1 in any of the bits of these registers has the effect of turning the pedestal off on the equivalent line when used in ntsc. a logic 1 in any of the bits of these registers ha s the effect of turning teletext on the equivale nt line when used in pal. field 1/3 pco6 pco5 pco3 pco1 pco4 pco2 pco0 pco7 line 17 line 16 line 15 line 14 line 13 line 12 line 11 line 10 pco14 pco13 pco11 pco9 pco12 pco10 pco8 pco15 line 25 line 24 line 23 line 22 line 21 line 20 line 19 line 18 field 1/3 field 2/4 pce6 pce5 pce3 pce1 pce4 pce2 pce0 pce7 line 17 line 16 line 15 line 14 line 13 line 12 line 11 line 10 pce14 pce13 pce11 pce9 pce12 pce10 pce8 pce15 line 25 line 24 line 23 line 22 line 21 line 20 line 19 line 18 field 2/4 02980-a-047 figure 48. pedestal control registers field 1/3 field 1/3 field 2/4 field 2/4 txo6 txo5 txo3 txo1 txo4 txo2 txo0 txo7 line 14 line 13 line 12 line 11 line 10 line 9 line 8 line 7 txo14 txo13 txo11 txo9 txo12 txo10 txo8 txo15 line 22 line 21 line 20 line 19 line 18 line 17 line 16 line 15 txe6 txe5 txe3 txe1 txe4 txe2 txe0 txe7 txe14 txe13 txe11 txe9 txe12 txe10 txe8 txe15 line 14 line 13 line 12 line 11 line 10 line 9 line 8 line 7 line 22 line 21 line 20 line 19 line 18 line 17 line 16 line 15 02980-a-048 figure 49. teletext control registers
adv7174/adv7179 rev. b | page 37 of 52 teletext request control register (tc07) bits: tc07Ctc00 address: sr4Csr0 = 19h teletext control register is an 8-bit-wide register (see figure 50 ). table 17. teletext request control register bit name bit no. description ttxreq rising edge control tc07Ctc04 these bits control the position of the rising edge of ttxreq. it can be programmed from 0 clock cycles to a maximum of 15 clock cycles (see figure 50 ). ttxreq falling edge control tc03Ctc00 these bits control the position of the falling edge of ttxreq. it can be programmed from zero clock cycles to a max of 15 clock cycles. this controls the active window for teletext data. increa sing this value reduces the amount of teletext bits below the default of 360. if bits tc03Ctc00 are 00h when bits tc07C tc04 are changed, the falling edge of ttxreq tracks that of the rising edge, i.e., the time between the falling and rising edge remains constant (see figure 49 ). cgms_wss register 0 (c/w0) bits: c/w07Cc/w00 address: sr4Csr0 = 16h cgms_wss register 0 is an 8-bit-wide register. figure 51 shows the operations under the control of this register. tc01 tc00 tc07 tc02 tc04 tc03 tc05 tc06 ttxreq rising edge control tc07 tc06 tc05 tc04 00 0 00 p c l k 0001 1111 1110 """" 1pclk "pclk 14 pclk 15 pclk ttxreq falling edge control tc03 tc02 tc01 tc00 0pclk 1pclk "pclk 14 pclk 15 pclk 00 0 0 0001 1111 1110 """" 02980-a-049 figure 50. teletext control register c/w07 c/w06 c/w05 c/w04 c/w03 c/w02 c/w01 c/w00 c/w07 wide screen signal control 0 disable 1 enable 0 disable 1 enable c/w05 cgms odd field control c/w06 cgms even field control 0 disable 1 enable c/w04 cgms crc check control 0 disable 1 enable c/w03 ? c/w00 cgms data bits 02980-a-050 figure 51. cgms_wss register 0 table 18. c/w0 bit description bit name bit no. description cgms data bits c/w03Cc/w00 these four data bits are the fi nal four bits of the cgms da ta output stream. note it is cgms data only in these bit positions, i. e., wss data does not share this location. cgms crc check con t rol c/w04 when this bit is enabled (1), the last six bits of the cgms data, i.e., the crc check sequence, are calculated internally by the adv 7174/adv7179. if this bit is disabled (0), the crc values in the register are output to the cgms data stream. cgms odd field control c/w05 when this bit is set (1), cgms is enabled for odd fields. note this is only valid in ntsc mode. cgms even field control c/w06 when this bit is set (1), cgms is enabled for even fields. note th is is only valid in ntsc mode. wss control c/w07 when this bit is set (1), wide screen si gnaling is enabled. note this is only valid in pal mode.
adv7174/adv7179 rev. b | page 38 of 52 cgms_wss register 1 (c/w1) bits: c/w17Cc/w10 address : sr4Csr0 = 17h cgms_wss register 1 is an 8-bit-wide register. figure 52 shows the operations under the control of this register. c/w17 c/w16 c/w15 c/w14 c/w13 c/w12 c/w11 c/w10 c/w15 ? c/w10 cgms/wss data bits c/w17 ? c/w16 cgms data bits 02980-a-051 figure 52. cgms_wss register 1 table 19. c/w1 bit description bit name bit no. description cgms/wss data bits c/w15Cc/w10 these bit locations are shared by cgms data and wss data. in ntsc mode, these bits are cgms data. in pal mode, these bits are wss data. cgms data bits c/w17Cc/w16 thes e bits are cgms data bits only. cgms_wss register 2 (c/w2) bits: c/w27Cc/w20 address: (sr4Csr00) = 18h cgms_wss register 2 is an 8-bit-wide register. figure 53 shows the operations under the control of this register. c/w27 c/w26 c/w25 c/w24 c/w23 c/w22 c/w21 c/w20 c/w27 ? c/w20 cgms/wss data bits 02980-a-052 figure 53. cgms_wss register 2 table 20. c/w2 bit description bit name bit no. description cgms/wss data bits c/w27Cc/w20 these bit locations are shared by cgms data and wss data. in ntsc mode, these bits are cgms data. in pal mode, these bits are wss data.
adv7174/adv7179 rev. b | page 39 of 52 appendix 1board design and layout considerations power planes the adv7174/adv7179 is a highly integrated circuit contain- ing both precision analog and high speed digital circuitry. it has been designed to minimize interference effects on the integrity of the analog circuitry by the high speed digital circuitry. it is imperative that these same design and layout techniques be applied to the system-level design so that high speed, accurate performance is achieved. figure 54 shows the analog interface between the device and monitor. the adv7174/adv7179 and any associated analog circuitry should have its own power plane, referred to as the analog power plane (v aa ). this power plane should be connected to the regular pcb power plane (v cc ) at a single point through a ferrite bead. this bead should be located within 3 inches of the adv7174/adv7179. the metallization gap separating the device power plane and board power plane should be as narrow as possible to minimize the obstruction to the flow of heat from the device into the general board. the layout should be optimized for lowest noise on the adv7174/adv7179 power and ground lines by shielding the digital inputs and providing good decoupling. the lead length between groups of v aa and gnd pins should be minimized to reduce inductive ringing. the pcb power plane should provide power to all digital logic on the pc board, and the analog power plane should provide power to all adv7174/adv7179 power pins and voltage reference circuitry. ground planes the ground plane should encompass all adv7174/adv7179 ground pins, voltage reference circuitry, power supply bypass circuitry for the adv7174/adv7179, the analog output traces, and all the digital signal traces leading up to the adv7174/ adv7179. the ground plane is the boards common ground plane. plane-to-plane noise coupling can be reduced by ensuring that portions of the regular pcb power and ground planes do not overlay portions of the analog power plane unless they can be arranged so that the plane-to-plane noise is common mode. l1 (ferrite bead) 5k 3.3 v (v cc ) 150 5k 3.3 v (v cc ) mpu bus 3?5, 35?39 0.1 f 0.01 f 0.1 f 3.3 v (v aa ) 0.1 f 3.3v (v aa ) 10k 3.3 v (v aa ) 27mhz clock (same clock as used by mpeg2 decoder) power supply decoupling for each power supply group 10 f 33 f gnd 3.3 v (v cc ) gnd alsb hsync field/vsync blank reset clock r set sdata sclock dac b dac c v aa v ref comp p7?p0 3.3 v (v aa ) 75 75 75 screset/rtc adv7174/adv7179 unused inputs should be grounded dac a 100 100 reset ttx ttxreq 100k 100k 3.3 v (v cc ) ttx ttxreq teletext pull-up and pull-down resistors should only be used if these pins are not connected 4k 3.3 v (v aa ) 100nf 24 28 29 21 22 31 16 1 30 32 23 13 14 15 20 34 33 02980-a-053 figure 54. recommended analog circuit layout
adv7174/adv7179 rev. b | page 40 of 52 supply decoupling for optimum performance, bypass capacitors should be in- stalled using the shortest leads possible, consistent with reliable operation, to reduce the lead inductance. best performance is obtained with 0.1 f ceramic capacitor decoupling. each group of v aa pins on the adv7174/adv7179 must have at least one 0.1 f decoupling capacitor to gnd. these capacitors should be placed as close to the device as possible. it is important to note that while the adv7174/adv7179 contains circuitry to reject power supply noise, this rejection decreases with frequency. if a high frequency switching power supply is used, the designer should pay close attention to reducing power supply noise and consider using a 3-terminal voltage regulator for supplying power to the analog power plane. digital signal interconnect the digital inputs to the adv7174/adv7179 should be isolated as much as possible from the analog outputs and other analog circuitry. also, these input signals should not overlay the analog power plane. due to the high clock rates involved, long clock lines to the adv7174/adv7179 should be avoided to reduce noise pickup. any active termination resistors for the digital inputs should be connected to the regular pcb power plane (v cc ) and not to the analog power plane. analog signal interconnect the adv7174/adv7179 should be located as close to the output connectors as possible to minimize noise pickup and reflections due to impedance mismatch. the video output signals should overlay the ground plane, not the analog power plane, to maximize the high frequency power supply rejection. digital inputs, especially pixel data inputs and clocking signals, should never overlay any of the analog signal circuitry and should be kept as far away as possible. for best performance, the outputs should each have a 75 load resistor connected to gnd. these resistors should be placed as close as possible to the adv7174/adv7179 to minimize reflections. the adv7174/adv7179 should have no inputs left floating. any inputs that are not required should be tied to ground. the circuit in figure 55 can be used to generate a 13.5 mhz waveform using the 27 mhz clock and the hsync pulse. this waveform is guaranteed to produce the 13.5 mhz clock in synchronization with the 27 mhz clock. this 13.5 mhz clock can be used if the 13.5 mhz clock is required by the mpeg decoder. this guarantees that the cr and cb pixel information is input to the adv7174/adv7179 in the correct sequence. note that the exposed metal paddle on the bottom side of the lfcsp package must be soldered to pcb ground for proper heat dissipation and also for electrical noise and mechanical strength benefits. d q ck d q ck clock hsync 13.5mhz 02980-a-054 figure 55. circuit to generate 13.5 mhz
adv7174/adv7179 rev. b | page 41 of 52 appendix 2closed captioning the adv7174/adv7179 supports closed captioning, conform- ing to the standard television synchronizing waveform for color transmission. closed captioning is transmitted during the blanked active line time of line 21 of the odd fields and line 284 of even fields. closed captioning consists of a 7-cycle sinusoidal burst that is frequency-locked and phase-locked to the caption data. after the clock run-in signal, the blanking level is held for 2 data bits and is followed by a logic 1 start bit. 16 bits of data follow the start bit. these consist of two 8-bit bytes, 7 data bits, and 1 odd parity bit. the data for these byte s is stored in closed captioning data registers 0 and 1. the adv7174/adv7179 also supports the extended closed captioning operation, which is active during even fields, and is encoded on scan line 284. the data for this operation is stored in closed captioning extended data registers 0 and 1. all clock run-in signals and timing to support closed captioning on lines 21 and 284 are automatically generated by the adv7174/adv7179. all pixel inputs are ignored during lines 21 and 284. fcc code of federal regulations (cfr) 47 section 15.119 and eia-608 describe the closed captioning information for lines 21 and 284. the adv7174/adv7179 uses a single buffering method. this means that the closed captioning buffer is only one byte deep, therefore there will be no frame delay in outputting the closed captioning data unlike other 2-byte deep buffering systems. the data must be loaded at least one line before (line 20 or line 283) it is outputted on line 21 and line 284. a typical implementation of this method is to use vsync to interrupt a microprocessor, which in turn loads the new data (two bytes) every field. if no new data is required for transmission, you must insert zeros in both the data registers; this is called nulling . it is also important to load control codes, all of which are double bytes, on line 21, or a tv cannot recognize them. if you have a message such as hello world, which has an odd number of characters, it is important to pad it out to an even number to get the end of the caption 2-byte control code to land in the same field. 50 ire 12.91 s s t a r t p a r i t y p a r i t y d0?d6 d0?d6 10.003 s 33.764 s 40 ire frequency = f sc = 3.579545mhz amplitude = 40 ire reference color burst (9 cycles) 7 cycles of 0.5035 mhz (clock run-in) 10.5 0.25 s two 7-bit + parity ascii characters (data) 27.382 s byte 0 byte 1 02980-a-055 figure 56. closed captioning waveform (ntsc)
adv7174/adv7179 rev. b | page 42 of 52 appendix 3copy generation management system (cgms) the adv7174/adv7179 supports the cgms, conforming to the standard. cgms data is transmitted on line 20 of the odd fields and on line 283 of the even fields. bits c/w05 and c/w06 control whether or not cgms data is output on odd and even fields. cgms data can only be transmitted when the adv7174/ adv7179 is configured in ntsc mode. the cgms data is 20 bits long, the function of each of these bits is as shown below. the cgms data is preceded by a reference pulse of the same amplitude and duration as a cgms bit (see figure 57 ). the bits are output from the configuration registers in the following order: c/w00 = c16, c/w01 = c17, c/w02 = c18, c/w03 = c19, c/w10 = c8, c/ w11 = c9, c/w12 = c10, c/w13 = c11, c/w14 = c12, c/ w15 = c13, c/w16 = c14, c/w17 = c15, c/w20 = c0, c/w21 = c1, c/w22 = c2, c/w23 = c3, c/w24 = c4, c/w 25 = c5, c/w26 = c6, c/w27 = c7. if bit c/w04 is set to a logic 1, the last six bits, c19Cc14, which comprise the 6-bit crc check sequence, are calculated automatically on the adv7174/adv7179 based on the lower 14 bits (c0Cc13) of the data in the data registers and output with the remaining 14 bits to form the complete 20 bits of the cgms data. the calculation of the crc sequence is based on the polynomial x 6 + x + 1 with a preset value of 111111. if c/w04 is set to a logic 0, all 20 bits (c0Cc19) are directly output from the cgms registers (no crc is calculated; it must be calculated by the user). function of cgms bits word 0 C6 bits word 1 C4 bits word 2 C4 bits crc C6 bits crc polynomial = x 6 + x + 1 (preset to 111111) table 21. bit 1Cbit 14 word bit function word 0 1 0 b1 aspect ratio 16:9 4:3 b2 display format letterbox normal b3 undefined b4, b5, b6 identification information about video and other signals, for example, audio word 1 b7, b8, b9, b10 identificati on signal incidental to word 0 word 2 b11, b12, b13, b14 identification si gnal and information incidental to word 0 crc sequence 11.2 s 2.235 s 20ns 49.1 s 0.5 s ref c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 c14 c15 c16 c17 c18 c19 100 ire 70 ire 0 ire ?40 ire 02980-a-056 figure 57. cgms waveform diagram
adv7174/adv7179 rev. b | page 43 of 52 appendix 4wide screen signaling (wss) the adv7174/adv7179 supports wss, conforming to the standard. wss data is transmitted on line 23. wss data can only be transmitted when the adv7174/ adv7179 is configured in pal mode. the wss data is 14 bits long, the function of each of these bits is as shown below. the wss data is preceded by a run-in sequence and a start code (see figure 58 ). the bits are output from the configuration registers in the following order: c/w20 = w0, c/w21 = w1, c/w22 = w2, c/w23 = w3, c/w24 = w4, c/w25 = w5, c/w26 = w6, c/w27 = w7, c/w10 = w8, c/ w11 = w9, c/w12 = w10, c/w13 = w11, c/w14 = w12, c/w15 = w13. if the bit c/w07 is set to a logic 1, it enables the wss data to be transmitted on line 23. the latter portion of line 23 (42.5 s from the falling edge of hsync ) is available for the insertion of video. function of wss bits table 22. bit 0Cbit 2 bit 3 is the odd parity check of bit 0Cbit 2 b0 b1 b2 b3 aspect ratio format position 0 0 0 1 4:3 full format not applicable 1 0 0 0 14:9 letterbox center 0 1 0 0 14:9 letterbox top 1 1 0 1 16:9 letterbox center 0 0 1 0 16:9 letterbox top 1 0 1 1 >16:9 letterbox center 0 1 1 1 14:9 full format center 1 1 1 0 16:9 not applicable not applicable table 23. bit 4Cbit 7 bit value description b4 0 1 camera mode film mode b5 0 1 standard coding motion adaptive color plus b6 0 1 no helper modulated helper b7 reserved b8 0 1 no teletext subtitles teletext subtitles b9Cb10 0, 0 no open subtitles 1, 0 subtitles in active image area 0, 1 subtitles out of active image area 1, 1 reserved b11 0 1 no surround sound information surround sound mode b12 reserved b13 reserved 11.0 s w0 w1 w2 w3 w4 w5 w6 w7 w8 w9 w10 w11 w12 w13 500mv run-in sequence start code active video 02980-a-057 38.4 s 42.5 s figure 58. wss waveform diagram
adv7174/adv7179 rev. b | page 44 of 52 appendix 5teletext teletext insertion t pd is the time needed by the adv7174/adv7179 to interpolate input data on ttx and insert it onto the cvbs or y outputs, such that it appears t synttxout = 10.2 s after the leading edge of the horizontal signal. time ttx del is the pipeline delay time by the source that is gated by the ttxreq signal in order to deliver ttx data. with the programmability offered with the ttxreq signal on the rising/falling edges, the ttx data is always inserted at the correct position of 10.2 s after the leading edge of horizontal sync pulse, thus enabling a source interface with variable pipe- line delays. the width of the ttxreq signal must always be maintained to allow the insertion of 360 (to comply with the teletext standard pal-wst) teletext bits at a text data rate of 6.9375 mbits/s. this is achieved by setting tc03Ctc00 to 0. the insertion window is not open if the teletext enable bit (mr35) is set to 0. teletext protocol the relationship between the ttx bit clock (6.9375 mhz) and the system clock (27 mhz) for 50 hz is () 027777.11075.6109375.6 75.6 4 6 6 27 = = ? ? ? ? ? ? mhz mhz thus, 37 ttx bits correspond to 144 clocks (27 mhz) and each bit has a width of almost four clock cycles. the adv7174/ adv7179 uses an internal sequencer and variable phase inter- polation filter to minimize the phase jitter and thus generate a band-limited signal that can be output on the cvbs and y outputs. at the ttx input, the bit duration scheme repeats after every 37 ttx bits or 144 clock cycles. the protocol requires that ttx bits 10, 19, 28, and 37 are carried by three clock cycles and all other bits by four clock cycles. after 37 ttx bits, the next bits with three clock cycles are 47, 56, 65, and 74. this scheme holds for all following cycles of 37 ttx bits until all 360 ttx bits are completed. all teletext lines are implemented in the same way. individual control of teletext lines is controlled by teletext setup registers. address and data run-in clock teletext vbi line 45 bytes (360 bits) ? pal 02980-a-058 figure 59. teletext vbi line programmable pulse edges t pd t pd cvbs/y hsync ttxreq ttx data t synttxout = 10.2 s t pd = pipeline delay through adv7174/adv7179 ttx del = ttxreq to ttx (programmable range = 4 bits [0?15 clock cycles]) t synttxout 10.2 s ttx del ttx st 02980-a-059 figure 60. teletext functionality
adv7174/adv7179 rev. b | page 45 of 52 appendix 6waveforms ntsc waveforms (with pedestal) 130.8 ire 100 ire 7.5 ire 0 ire ?40 ire peak composite ref white sync level blank level 1268.1mv 1048.4mv 387.6mv 334.2mv 48.3mv 714.2mv black level 02980-a-060 figure 61. ntsc composite video levels 100 ire 7.5 ire 0 ire ?40 ire ref white sync level blank level 1048.4mv 387.6mv 334.2mv 48.3mv black level 714.2mv 02980-a-061 figure 62. ntsc luma video levels 650mv 335.2mv 963.8mv 0mv peak chroma blank/black level 286mv (p-p) peak chroma 629.7mv (p-p) 02980-a-062 figure 63. ntsc chroma video levels 100 ire 7.5 ire 0 ire ? 40 ire ref white sync level blank level 1052.2mv 387.5mv 331.4mv 45.9mv 720.8mv black level 02980-a-063 figure 64. ntsc rgb video levels
adv7174/adv7179 rev. b | page 46 of 52 ntsc waveforms (without pedestal) 130.8 ire 100 ire 0 ire ?40 ire peak composite ref white sync level blank/black level 1289.8m v 1052.2mv 338mv 52.1mv 714.2mv 02980-a-064 figure 65. ntsc composite video levels 100 ire 0 ire ? 40 ire ref white sync level blank/black level 1052.2mv 338mv 52.1mv 714.2mv 02980-a-065 figure 66. ntsc luma video levels 650mv 299.3mv 978mv 0mv peak chroma blank/black level 286mv (p-p) peak chroma 694.9mv (p-p) 02980-a-066 figure 67. ntsc chroma video levels 100 ire 0 ire ? 40 ire ref white sync level blank/black level 715.7mv 1052.2mv 336.5mv 51mv 02980-a-067 figure 68. ntsc rgb video levels
adv7174/adv7179 rev. b | page 47 of 52 pal waveforms 1288.6mv 1051mv 351mv 51mv peak composite ref white sync level blank/black level 700mv 02980-a-068 figure 69. pal composite video levels 1051m v 351mv 51mv ref white sync level blank/black level 700mv 02980-a-069 figure 70. pal luma video levels 650mv 317.7mv 989.7mv 0mv peak chroma blank/black level 300mv (p-p) 672mv (p-p) peak chroma 02980-a-070 figure 71. pal chroma video levels 1051m v 351mv 51mv ref white sync level blank/black level 700mv 02980-a-071 figure 72. pal rgb video levels
adv7174/adv7179 rev. b | page 48 of 52 pb pr waveforms betacam leve l 0mv +171mv +334mv +505mv 0mv ?171mv ?334mv ?05mv white yellow cyan green magent a red blue black 02980-a-072 figure 73. ntsc 100% color bars, no pedestal pb levels betacam level 0mv +158mv +309mv +467mv 0mv ?158mv ?309mv ?467mv white yellow cyan green magent a red blue black 02980-a-073 figure 74. ntsc 100% color bars with pedestal pb levels smpte level 0mv +118mv +232mv +350mv 0mv ?118mv ?232mv ?350mv white yellow cyan green magenta red blue black 02980-a-074 figure 75. pal 100% color bars, pb levels betacam level 0mv +82mv +423mv +505mv 0mv ?82mv ?505mv ?423mv white yellow cyan green magent a red blue black 02980-a-075 figure 76. ntsc 100% color bars, no pedestal pr levels betacam level 0mv +76mv +391mv +467mv 0mv ?76mv ?467mv ?391mv white yellow cyan green magent a red blue black 02980-a-076 figure 77. ntsc 100% color bars with pedestal pr levels s mpte level 0mv +57mv +293mv +350mv 0mv ?57mv ?350mv ?293mv white yellow cyan green magent a red blue black 02980-a-077 figure 78. pal 100% color bars, pr levels
adv7174/adv7179 rev. b | page 49 of 52 appendix 7optional output filter if an output filter is required for the cvbs, y, uv, chroma, and rgb outputs of the adv7174/adv7179, the filter shown in figure 79 can be used. plots of the filter characteristics are shown in figure 80 . an output filter is not required if the outputs of the adv7174/adv7179 are connected to most analog monitors or analog tvs. however, if the output signals are applied to a system where sampling is used (e.g., digital tvs), then a filter is required to prevent aliasing. 1.8 h 75 270pf 22pf display device z 0 = 75 330pf filter i/p 75 02980-a-078 figure 79. output filter frequency (hz) 0 80 100k magnitude (db) 70 60 50 40 30 20 10 1m 10m 100m 02980-a-079 figure 80. output filter plot
adv7174/adv7179 rev. b | page 50 of 52 appendix 8recommended register values the adv7174/adv7179 registers can be set depending on the user standard required. the power-on reset values can be found in figure 37 . the following examples give the various register formats for several video standards. in each case, the output is set to compos- ite output with all dacs powered up and with the input control disabled. additionally, the burst and blank color information is enabled on the output, and the internal color bar generator is switched off. in the examples shown, the timing mode is set to mode 0 in slave format. tr02Ctr00 of the timing register 0 control the timing modes. for a detailed explanation of each bit in the command registers, refer to the section. tr07 should be toggled after setting up a new timing mode. timing register 1 provides additional control over the position and duration of the timing signals. in the examples, this register is programmed in default mode. register programming table 24. pal b/d/g/h/i (f sc = 4.43361875 mhz) address description data 00h mode register 0 05h 01h mode register 1 10h 02h mode register 2 00h 03h mode register 3 00h 04h mode register 4 00h 07h timing register 0 00h 08h timing register 1 00h 09h subcarrier frequency register 0 cbh 0ah subcarrier frequency register 1 8ah 0bh subcarrier frequency register 2 09h 0ch subcarrier frequency register 3 2ah 0dh subcarrier phase register 00h 0eh closed captioning ext register 0 00h 0fh closed captioning ext register 1 00h 10h closed captioning register 0 00h 11h closed captioning register 1 00h 12h pedestal control register 0 00h 13h pedestal control register 1 00h 14h pedestal control register 2 00h 15h pedestal control register 3 00h 16h cgms_wss register 0 00h 17h cgms_wss register 1 00h 18h cgms_wss register 2 00h 19h telext request control register 00h 0fh closed captioning ext register 1 00h 10h closed captioning register 0 00h 11h closed captioning register 1 00h 12h pedestal control register 0 00h 13h pedestal control register 1 00h 14h pedestal control register 2 00h 15h pedestal control register 3 00h 16h cgms_wss register 0 00h 17h cgms_wss register 1 00h 18h cgms_wss register 2 00h 19h teletext request control register 00h table 25. pal n (f sc = 4.43361875 mhz) address description data 00h mode register 0 05h 01h mode register 1 10h 02h mode register 2 00h 03h mode register 3 00h 04h mode register 4 00h 07h timing register 0 00h 08h timing register 1 00h 09h subcarrier frequency register 0 cbh 0ah subcarrier frequency register 1 8ah 0bh subcarrier frequency register 2 09h 0ch subcarrier frequency register 3 2ah 0dh subcarrier phase register 00h 0eh closed captioning ext register 0 00h 0fh closed captioning ext register 1 00h 10h closed captioning register 0 00h 11h closed captioning register 1 00h 12h pedestal control register 0 00h 13h pedestal control register 1 00h 14h pedestal control register 2 00h 15h pedestal control register 3 00h 16h cgms_wss register 0 00h 17h cgms_wss register 1 00h 18h cgms_wss register 2 00h 19h teletext request control register 00h
adv7174/adv7179 rev. b | page 51 of 52 table 26. pal-60 (f sc = 4.43361875 mhz) address description data 00h mode register 0 04h 01h mode register 1 10h 02h mode register 2 00h 03h mode register 3 00h 04h mode register 4 00h 07h timing register 0 00h 08h timing register 1 00h 09h subcarrier frequency register 0 cbh 0ah subcarrier frequency register 1 8ah 0bh subcarrier frequency register 2 09h 0ch subcarrier frequency register 3 2ah 0dh subcarrier phase register 00h 0eh closed captioning ext register 0 00h 0fh closed captioning ext register 1 00h 10h closed captioning register 0 00h 11h closed captioning register 1 00h 12h pedestal control register 0 00h 13h pedestal control register 1 00h 14h pedestal control register 2 00h 15h pedestal control register 3 00h 16h cgms_wss register 0 00h 17h cgms_wss register 1 00h 18h cgms_wss register 2 00h 19h teletext request control register 00h table 27. ntsc (f sc = 3.5795454 mhz) address description data 00h mode register 0 00h 01h mode register 1 10h 02h mode register 2 00h 03h mode register 3 00h 04h mode register 4 10h 07h timing register 0 00h 08h timing register 1 00h 09h subcarrier frequency register 0 1eh 1 0ah subcarrier frequency register 1 7ch 0bh subcarrier frequency register 2 f0h 0ch subcarrier frequency register 3 21h 0dh subcarrier phase register 00h 0eh closed captioning ext register 0 00h 0fh closed captioning ext register 1 00h 10h closed captioning register 0 00h 11h closed captioning register 1 00h 12h pedestal control register 0 00h 13h pedestal control register 1 00h 14h pedestal control register 2 00h 15h pedestal control register 3 00h 16h cgms_wss register 0 00h 17h cgms_wss register 1 00h 18h cgms_wss register 2 00h 19h teletext request control register 00h 1 on power-up, this register is set to 16h. 1eh should be written here for correct f sc .
adv7174/adv7179 rev. b | page 52 of 52 outline dimensions 1 40 10 11 31 30 21 20 bottom view 4.25 4.10 sq 3.95 top view 6.00 bsc sq pin 1 indicato r 5.75 bsc sq 12 max 0.30 0.23 0.18 0.20 ref seating plane 1.00 0.85 0.80 0.05 max 0.02 nom coplanarity 0.08 0.80 max 0.65 typ 4.50 ref 0.50 0.40 0.30 0.50 bsc pin 1 indicator 0.60 max 0.60 max 0.25 min compliant to jedec standards mo-220-vjjd-2 figure 81. 40-lead lead frame chip scale package [lfcsp_vq] 6 mm 6 mm body, very thin quad (cp-40-1) dimensions shown in millimeters note that the exposed metal paddle on the bottom side of the lfcsp package must be soldered to pcb ground for proper heat dissi pation and also for noise and mechanical strength benefits. ordering guide model temperature range package description package option adv7179kcp 1 0c to 70c 40-lead lead frame chip scale package [lfcsp_vq] cp-40-1 adv7179kcp-reel 1 0c to 70c 40-lead lead frame chip scale package [lfcsp_vq] cp-40-1 adv7179kcpz 2 0c to 70c 40-lead lead frame chip scale package [lfcsp_vq] cp-40-1 adv7179kcpz-reel 2 0c to 70c 40-lead lead frame chip scale package [lfcsp_vq] cp-40-1 adv7179bcp 1 ?40c to +85c 40-lead lead frame chip scale package [lfcsp_vq] cp-40-1 adv7179bcp-reel 1 ?40c to +85c 40-lead lead frame chip scale package [lfcsp_vq] cp-40-1 adv7179bcpz 2 ?40c to +85c 40-lead lead frame chip scale package [lfcsp_vq] cp-40-1 adv7179bcpz-reel 2 ?40c to +85c 40-lead lead frame chip scale package [lfcsp_vq] cp-40-1 adv7179wbcpz 2, 3 ?40c to +85c 40-lead lead frame chip scale package [lfcsp_vq] cp-40-1 adv7179wbcpzCreel 2, 3 ?40c to +85c 40-lead lead frame chip scale package [lfcsp_vq] cp-40-1 adv7174kcp 1 0c to 70c 40-lead lead frame chip scale package [lfcsp_vq] cp-40-1 adv7174kcp-reel 1 0c to 70c 40-lead lead frame chip scale package [lfcsp_vq] cp-40-1 adv7174kcpz 2 0c to 70c 40-lead lead frame chip scale package [lfcsp_vq] cp-40-1 adv7174kcpz-reel 2 0c to 70c 40-lead lead frame chip scale package [lfcsp_vq] cp-40-1 adv7174bcp 1 ?40c to +85c 40-lead lead frame chip scale package [lfcsp_vq] cp-40-1 adv7174bcp-reel 1 ?40c to +85c 40-lead lead frame chip scale package [lfcsp_vq] cp-40-1 adv7174bcpz 2 ?40c to +85c 40-lead lead frame chip scale package [lfcsp_vq] cp-40-1 adv7174bcpz-reel 2 ?40c to +85c 40-lead lead frame chip scale package [lfcsp_vq] cp-40-1 adv7174wbcpz 2, 3 ?40c to +85c 40-lead lead frame chip scale package [lfcsp_vq] cp-40-1 adv7174wbcpz-reel 2, 3 ?40c to +85c 40-lead lead frame chip scale package [lfcsp_vq] cp-40-1 eval-adv7179ebz 2 evaluation board eval-adv7174ebz 2 evaluation board 1 not recommended for new designs. 2 z = rohs compliant part. 3 automotive product. purchase of licensed i 2 c components of analog devices or one of its sublicensed associated companies conveys a license for the purchaser under the phi lips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. ?2002C2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d02980-0-4/09(b)

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